Having problem with FOR LOOP which leads to endless loop in system verilog

SystemVerilog
2

In reply to deepak_sadasivam_uvm:


add extra indx ques , loop through it to delete the index.
module tb_top();
int num_q[$] = '{0,1,2,3,4,5,6,7,8,9,10};
int del_q[$] = '{1,2};
int idx[$]; // index queue 
initial
begin
$display("num_q_size=%0d",num_q.size());
 
  foreach(del_q[i]) begin 
    idx = num_q.find_index with (item == del_q[i]);     
    if(idx.size != 0 ) begin
    foreach(idx[i]) begin // loop through index value. 
      num_q.delete(idx[i]); // delete the index
    end 
    end 
  end 
  $display("value of num_q=%p",num_q);
end
endmodule