Having instances of Both Child class and Parent class within a module

SystemVerilog
, , , ,
2

move the instance declaration before the procedural code.



module tb;
  initial begin
     childclass c1;
    parentclass p1 = new;
    p1.set(55,'h900);
    p1.get;
    p1.set_outside(66, 'h1000);
    p1.get_outside();
 
      // IS SOMETHING WRONG WITH THIS LINE???
    //c1.set_rd_wr("READ");
    //c1.get_rd_wr;
 
  end
endmodule