Getting this kind of warning :: Non-existent associative array entry. Returning default value

SystemVerilog
,
1

While running the below code i am getting the warning as i have mentioned above :

typedef enum bit {vlsm0,vlsm1} vlsm_type;
typedef enum bit[1:0] {almp_flit,io_flit,null_flit,null_flit_eds} flit_type;
//typedef class flit_c;
class flit_c;
rand vlsm_type vlsm;
rand flit_type flit;
endclass : flit_c



class state;
int flit_cnt[vlsm_type][flit_type] = ;

function void call(flit_c pkt);
flit_cnt[pkt.vlsm][pkt.flit]++;
$display("cnt is for flit_cnt[%s][%s] = %0d",pkt.vlsm,pkt.flit,flit_cnt[pkt.vlsm][pkt.flit]);
endfunction : call
endclass : state



module my_m;
initial begin
state state_c;
flit_c flit_cc;
state_c = new;
flit_cc = new;
repeat(4) begin
flit_cc.randomize();
state_c.call(flit_cc);
end
end
endmodule

HERE is the EDA link for same Code : Edit code - EDA Playground

2

In reply to d_g:

This is an expected warning as you are attempting to access an associative array member which doesn’t exist and that you will be getting the default value.

You could first check if the entry exists prior to attempting to access it to avoid the error.

3

In reply to cgales:
int flit_cnt[vlsm_type][flit_type] ; What should i assign here to avoid the warning?

4

In reply to d_g:

You cam use an assignment pattern with a default element. Since this a 2-D associative array, it needs to be specified as a set of nested defaults.

int flit_cnt[vlsm_type][flit_type] = '{default:'default:0}};

See section 7.8.7 Allocating associative array elements in the IEEE 1800-2017 SystemVerilog LRM for more information.