Getting the below syntax error

SystemVerilog
,
1

please help me to fix this error and let me know what is meant by Systemverilog mode?

Syntax error
Following verilog source has syntax error :
$urandom_range usage required SystemVerilog mode
“apb_v3_sram.v”, 112:token is ‘(’
wait_cyc_limit=$urandom_range(MIN_RAND_WAIT_CYC,MAX_RAND_WAIT_CYC);

2

In reply to Ramyarani:

Because even after 20 years some people are too pessimistic to adopt SystemVerilog, tools require the your files have a *.sv extension to be recognized as SystemVerilog syntax. Files with *.v are restricted to legacy Verilog syntax.