In reply to subbarao:
That’s correct what you are seeing. In 1 clock cycle you are passing the address and in the following clock cycle you see the read data, because it is sampled by 1 clock cycle. I do not understand your problem.
In reply to subbarao:
That’s correct what you are seeing. In 1 clock cycle you are passing the address and in the following clock cycle you see the read data, because it is sampled by 1 clock cycle. I do not understand your problem.