In reply to drogoff:
In reply to dave_59:
Yep - that was it. This also explains why I see examples of SV Interfaces with the signals declared as wires and not logic. I couldn’t figure out why this was being done since, with modports, no signal was bidirectional or multiply driven. Now it makes sense although it’s a bit ugly.
Dave, this solution of using wires just hit a speed bump. In one of my agents using the interface and clocking blocks, I need to look for an input signal and change an output signal in the same clock cycle. This is to model the RTL which is combinatorial. I can’t figure out a legal way to do this. I tried driving my_vif.signal_a directly to avoid the clocking block delay but got an error since signal_a is defined as a wire in the interface. I also tried using $deposit, but this gave an error since the signal is automatic.
So, any suggestion on modelling one output signal in an interface being combinatorial?
Thanks,
David