Getting error in assertion

SystemVerilog
,
1

Hi,
I am writing following assertion to check that address has incremented properly in between two events. The events correspond to the increasing LINE NUMBER. I am getting an error. Please suggest if I am doing something wrong.

property REGMODE_STRIDE;

logic [39:0] addr0;
logic [39:0] addr1;
logic [39:0] addr2;
@(posedge tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.I_SENSOR_RX_REGBANK.CLK) (tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.I_SENSOR_RX_REGBANK.SRX_LINE_COUNT[0], addr0 = tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.SRX_AXI_AWADDR[39:0]) ## [0:$] (tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.I_SENSOR_RX_REGBANK.SRX_LINE_COUNT[1] ==1) |-> ((addr1 - addr0) == 40’h5000);

endproperty

REGMODE_CHECK: assert property (@(posedge tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.I_SENSOR_RX_REGBANK.CLK) REGMODE_STRIDE);

The error is

Error-[SVA-IULV] Illegal use of local variable
/user/axmm/Perforce/amit.mishra_hhgw01_5170_1304/imgworks/hw/soc_ip/sensor_rx/DEV/RBJ/src/test/generic_tb/assert_macros.sv, 170
Illegal use of local variable, variable ‘addr1’ in assertion
‘REGMODE_CHECK8’.

Please suggest.

2

In reply to Amit Kumar Mishra:

Small correction in the assertion name typo

REGMODE_CHECK8: assert property (@(posedge tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.I_SENSOR_RX_REGBANK.CLK) REGMODE_STRIDE);

3

In reply to Amit Kumar Mishra:

Hi, I have been able to solve it.

property REGMODE_STRIDE;

logic [39:0] addr0;
logic [39:0] addr1;
logic [39:0] addr2;

@(posedge tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.I_SENSOR_RX_REGBANK.CLK) ((tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.I_SENSOR_RX_REGBANK.SRX_LINE_COUNT[0] && tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.SRX_AXI_AWVALID && tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.SRX_AXI_AWREADY), addr0 = tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.SRX_AXI_AWADDR[39:0]) |-> ## [0:$] ((tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.I_SENSOR_RX_REGBANK.SRX_LINE_COUNT[1] && tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.SRX_AXI_AWVALID && tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.SRX_AXI_AWREADY), addr1 = tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.SRX_AXI_AWADDR[39:0]) |-> ((addr1 - addr0) == 40’h5000);

endproperty

REGMODE_CHECK8 : assert property (@(posedge tb_sensor_rx_top.i_tb_sensor_rx.i_sensor_rx.I_SENSOR_RX_REGBANK.CLK) REGMODE_STRIDE);