Hello everyone, I am a newbie in uvm. I am trying to reach interface signals in uvm_test. In below you can see what did I do for that but I get the following error. Can anyone help me to solve this problem? Thanks. module testbench; v_interface if0(clk, reset); initial begin …

In reply to Ankelih : There are many typos in the code that you have shown. When debugging issues with uvm_config_db, every character counts. You are doing the set() to the context “uvm_test_top_env.agt0”, but the get() is from the context “uvm_test_top”. In the set(), the null string replaces u…

IMPORTANT NOTICE: Please be advised that the Verification Academy Forums will be offline for scheduled maintenance on Sunday, November 9th at 1:00 US/Pacific.

Verification Academy

Get Virtual Interface In uvm_test

UVM

Ankelih April 21, 2022, 3:44pm 3

In reply to chr_sue:

I used it as example. I will edit post.