Does VCS need special switch to compile this code?
It is giving this error…
Error-[SE] Syntax error
Following verilog source has syntax error :
“…/sim_files/mdio/mdio_incr_sequence.sv”, 12: token is ‘const’
constraint r_delta { dev_addr > const’(dev_addr);}
^
SystemVerilog keyword ‘const’ is not expected to be used in this context.