Generate for assign statement -> how to?

SystemVerilog
,
3

In reply to dave_59:

will the following work?

// macro
`define sram_rdy(i)  sram``i.rdy
// sram_rdy
genvar i;
reg tmp = sram_rdy(0);
generate for (i=1;i<8;i=i+1)
  tmp = tmp & sram_rdy(i);   
end
endgenerate
assign sram_rdy = tmp;

Is the above code synthesizable?