Guys,
How do we implement randc ?
Basically, how do you generate cyclic random, without using randc keyword?
One solution: Store the generated values and compare until new value generated. Initially okay, but later would be problem.
I’m looking for feasible solution.
Any algorithm or system verilog will be appreciated.
John
John,
This is usually a quiz we provide to our VSV training (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) attendees at CVC. I would be glad to share the code on separate email than here just to ensure our future attendees have the much needed coding practice. If you like to receive the code, contact us via: http://www.cvcblr.com/about_us
BTW - why do you need to do this? I thought most of the tools support randc anyway.
Regards
Ajeetha, CVC
Basically, how do you generate cyclic random, without using randc keyword?
The following is the hard way; however, it is synthesizable and that can be used for Built-In Self-Test (BIST).
http://systemverilog.us/ → VHDL MODELS & PAPERS → lfsrstd.vhd Package: Linear Feedback Shift Register
– Source of : “Built-In Test for VLSI: Pseudorandom Techniques”,
– equations : Paul H. Bardell, William H. McAnney, Jacob Savir,
– : John Wiley and Sons, 1987.
– : the polynomials for degrees 2 through 300.
– :
– Synthesis : This code is synthesizable. P
From the searches on (LFSR chip signature self-test)
Signature analysis registers are often used in combination with standard LFSRs for on-chip selftest of VLSI circuits. The idea, explained in more detail in the following applet, is to use a first standard LFSR to generate a long sequence of pseudo-random input data for a block of logic. The outputs of the block of logic are connected to the data inputs of a second signature analysis register. After running both registers for a predefined number of clock cycles, the result value of the signature analysis register is read-out and compared with the constant ‘golden’ signature value calculated beforehand for the intact circuit. If the signatures differ, the block of logic is known to be defect, while matching signatures indicate that the block of logic is working (with a very high-probability). Two major advantages of using LFSRs for the pattern generation and signature analysis are their low cost and high operating frequency.
LFSR-based signature analysis register (8-bit) …A variant of the signature analysis register, the so-called BILBO, can be used in different operating modes as each of a standard D-type register, standard shift-register, LFSR-based pattern generator, and LFSR-based signature analysis register.
Built-In Self Test In Self Test
www.cs.uoi.gr/~tsiatouhas/CCD/Section_8_3-2p.pdf
Feb 5, 2012 - In built-in self test the test vectors are generated inside the chip and they are … operation the LFSR’s contents is the signature of the circuit.
Ben Cohen http://systemverilog.us
Hi,
Generate an array with values 0 to 15 (if you want to generate 0 to 15 randomly cyclically).
then call array.shuffle();
Then read values array[i], i from 0 to 15.
After reading the array 16 times call array.shuffle() again.
Not sure this helps.
Thanks.
Try https://leventozturk.com/engineering/crc/
It generates code for lfsr and generates lfsr outputs.