Generate a macro define which name is a concatenation of another macro text

SystemVerilog
2

In reply to rodrigoportella:

Section 22.5.1 of the SystemVerilog LRM describes the use of `define:

A `` delimits lexical tokens without introducing white space, allowing identifiers to be constructed from arguments. For example:


    `define append(f) f``_master

An example of using this `append macro is:


    `append(clock)

This example expands to:


    clock_master