Generate a macro define which name is a concatenation of another macro text

SystemVerilog
1

So, suppose I have a macro define that comes from somewhere else and can take many integer values:
`define NUM_OF_THINGS 32

Now, what I want to have is another macro define that can concatenate that ‘32’ into its name:
`define THINGS_32

How do I generate the second macro based on the value of the first?

2

In reply to rodrigoportella:

Section 22.5.1 of the SystemVerilog LRM describes the use of `define:

A `` delimits lexical tokens without introducing white space, allowing identifiers to be constructed from arguments. For example:


    `define append(f) f``_master

An example of using this `append macro is:


    `append(clock)

This example expands to:


    clock_master
3

The reason I want to have the second macro is to actually include/exclude portions of code using an ifdef. Therefore NUM_OF_THINGS can take values like 32, 16 or 4 and I want to test:


`ifdef THINGS_32
... instantiate a special class
`elsif THINGS_16
... intantiate another class
`elsif THINGS_4
do nothing
`endif

in order to include or exclude functionality.
Would that be possible?

4

In reply to rodrigoportella:

You cannot derive a macro name by using the contents of another macro.

There might be a completely different way to approach what you want to do. Please explain with a minimal example what you in the end generated.

5

Hi rodrigoportella,

You can refer below code :
// Code your testbench here
// or browse Examples
`define NUM_OF_THINGS 32

define XYZ \ define THINGS_```NUM_OF_THINGS 1

`XYZ
module top;

initial begin
$display(`THINGS_32);
end

endmodule