Generate a clock of 8MHz and stop it when condition is true and start it after if condition is true after a clock delay

UVM
,
1

I want to generate a clock with 8 MHz frequency and stop the clock when condition is true and restart the clock again after certain conditions after a delay.

tb_clk = 1'b0;
wait(top_smps_state == 3'b001)
tb_clk = 1'b1;
forever begin
  if(top_hsesel==0 && top_hsesel_done==0)begin
    #FREQ_8MHZ tb_clk = ~tb_clk;
  end else if(top_hsesel==1 && top_hsesel_done==1)begin
    @(posedge top_clk_hse);
    #FREQ_8MHZ tb_clk = ~tb_clk;
  end else begin
    tb_clk=0;
  end
end

This code is hanging . Please provide a solution

2

In reply to kulua:

Your code is hanging because whenever the condition top_hsesel==1 && top_hsesel_done==0 or top_hsesel==0 && top_hsesel_done==1 occurs, the forever goes into an infinite zero-delay loop.

It is hard to give you a solution because your code is much more complicated than your description. (There are 3 conditional expressions in your code and 2 in your description, and no mention of @(posedge top_clk_hse) ). May this will work.

forever begin : outer_loop
  tb_clk = 1'b0;
  wait(top_smps_state == 3'b001)
  tb_clk = 1'b1;
  forever begin : inner_loop
    if(top_hsesel==0 && top_hsesel_done==0)begin
      #FREQ_8MHZ tb_clk = ~tb_clk;
    end else if(top_hsesel==1 && top_hsesel_done==1)begin
      @(posedge top_clk_hse);
      #FREQ_8MHZ tb_clk = ~tb_clk;
    end else begin
      break; // out of inner loop
    end
  end : inner_loop
end : outer_loop

You could sill get into am infinite loop hang if the condition (top_smps_state == 3’b001) is true when you break out of the inner loop.