Generate a 2/3 clock frequency in TB using System Verilog and Verilog

SystemVerilog
,
2

In reply to sk7799:

At it’s most basic.

A typical 50% duty implementation:

initial begin
   clk = 0;
   forever #10 clk = ~clk;
end

Could be implemented:

initial begin
   clk = 0;
   forever begin
       #5;
       clk = 1;
       #5;
       clk = 0;
   end
end

So a 66.6% duty, is simply:

initial begin
   clk = 0;
   forever begin
      #3.333;
      clk = 1;
      #6.667;
      clk = 0;
   end
end

Then put this in an interface, embellish it with enable/disable, glitch-free frequency changes, jitter, etc.