Hello
I am a former cadence user, non moving to Questa, dealing with SV verification of a VHDL RTL design. I cannot use $signal_force to force SV structs or classes to a VHDL record signal or port inner in the VHDL RTL (please correct me if I am wrong) I want to write a general-purpose function / class for doing this
the SV verification struct
typedef struct packed {
bit irq_req_en;
bit unsigned [3:0] rd_unf_guard;
} control_t;
The VHDL RTL record (declared in a package)
type control_t is record
irq_req_en: std_logic;
rd_unf_guard : std_logic_vector(3 downto 0);
end record reg_type_t;
Is there a way to write a paramenteerized class having a struct type as a paramenter and then write a task which access individually the struct member? I understand this is challenging and probably not permitted by SV but I want to give a try
I am basically looking for some efficient and elegan methodolgy for doing this
thanks much