Functional coverage

SystemVerilog
,
1

Hi All, please go through code below:

covergroup cg @(cov_ev);
coverpoint addr{
               bins min[] = {32'h0000_0000:32'h0000_FFFF};
               bins mid[] = {32'h1_0004:32'h1000_FFFF};
               bins max[] = {32'hF000_0000:32'hFFFF_FFF0};
               }
endgroup

i am getting the error as the range is overlapping for the bins min and mid.
can anyone suggest me the solution for the overlapping range in min and mid.
regards,
vinay

2

In reply to kumar-vin:

I’m getting a different error. You are missing 's around your ranges. Also addr needs to be at least 30 bits.

3

In reply to dave_59:
Hi dave,

addr is declared as bit[31:0] addr; // it is a class property

covergroup cg @(cov_ev);
coverpoint addr{
bins min = {[32’h0000_0000:32’h0000_FFFF]};
bins mid = {[32’h1_0004:32’h1000_FFFF]};
bins max = {[32’hF000_0000:32’hFFFF_FFF0]};
}
endgroup

4

In reply to kumar-vin:

Hi All, please go through code below:

covergroup cg @(cov_ev);
coverpoint addr{
bins min[] = {32'h0000_0000:32'h0000_FFFF};
bins mid[] = {32'h1_0004:32'h1000_FFFF};
bins max[] = {32'hF000_0000:32'hFFFF_FFF0};
}
endgroup

i am getting the error as the range is overlapping for the bins min and mid.
can anyone suggest me the solution for the overlapping range in min and mid.
regards,
vinay

bins min[] = {[32'h0000_0000:32'h0000_FFFF]};

Isn’t it creating 65535 different bins? I think your intention is to create 1 bin for min range. If that is the case you should omit [] from the declaration and make it

bins min = {[32'h0000_0000:32'h0000_FFFF]};