Functional Coverage: Sampling RTL signals in a hierarchy (gives error)

When you use the bind construct, the syntax of bind instance should look exactly like it would if you had written it inside the target module. And the syntax of the module being bound uses normal Verilog syntax rules as well; you cannot have a port defined as a hierarchical reference. So change it to

module dut_cov_berc #(...)
(
input [PCT_DEPTH-1:0] pct_err_status_vec,
........
)

Then change your bind statement to

bind dut_berc
     dut_cov_berc #()
   FUNC_COVERAGE          (.pct_err_status_vec(u_dut_berc_cmd.pct_err_status_vec),.*);

I suspect you may be trying to access signals from many different levels of your DUT hierarchy. so instead of having a single dut_cov_berc module, you should break it up into several modules with separate bind statements that bind deeper into the hierarchy of your DUT. For example, you could change the bind statement above to

bind u_dut_berc.u_dut_berc_cmd
     dut_cov_berc #()
   FUNC_COVERAGE          (.*);