Functional Coverage: generate ignore bins at start of sim

SystemVerilog
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2

In reply to chintanm86:
You did not explain how the ma_cov class would know which slaves are to be ignored. However the covergroup feature you want is a bin set expression. You can populate an array with the slaves that are accessible and use the array when declaring the covergroup.

covergroup cg();
    option.per_instance = 1;
    m_slave: coverpoint slave_list_enum {
        bins slvs_b[] = { master_slave_list };
    }
endgroup

function new (string name, uvm_component parent);
   master_slave_list = // needs to be set before cg construction.
   cg = new();
   cg.set_inst_name(name); // sets the inst name as current master
endfunction
endclass