Function with variable input buswidth

SystemVerilog
,
5

In reply to hk123:

I was looking to see more of what you really wanted to do in function abc. But based on what you have shown, you could do:

module top;
virtual class C #(type T);
   static function void abc(input T data0, data1);
            $display("The value of data:%h", data0^data1);
   endfunction
endclass
task a();
  bit [5:0]a0, b0;
  C#(type(a0))::abc(a0,b0);
endtask
 
task b();
  bit [10:0]a0, b0;
  C#(type(a0))::abc(a0,b0);
endtask
 
task c();
  bit [128:0]a0, b0;
  C#(type(a0))::abc(a0,b0);
endtask
  initial begin
    a;b;c;
  end
endmodule