Function with variable input buswidth

SystemVerilog
,
4

In reply to dave_59:

Dave & Rsignori92,
Here is the sample snippet of code I’m trying to do:


task a();
  bit [5:0]a0, b0;
   abc(a0,b0);
endtask

task b();
  bit [10:0]a0, b0;
   abc(a0,b0);
endtask

task c();
  bit [128:0]a0, b0;
   abc(a0,b0);
endtask

    function void abc(input bit[5:0] data0, input bit[5:0]data1) // Here i want the flexibility to vary the bit width of inputs
            $display("The value of data:%h", data0^data1);
    endfunction