Function in Constraints-Solver Failed

SystemVerilog
,
1

I am trying to constraint the value of a rand variable in my class through a function but the below code results in solver error. Could someone please tell where exactly I am making a mistake here.

class sample;
  
  rand bit[7:0] x;
  
  constraint xcv{
    x == ret(x); 
  }
  
  function bit[7:0] ret(input bit[7:0] k);
    bit[7:0] count = 8'b0010;
    return count;
  endfunction
  
endclass


module tb;
  
  sample s;
  
  
  initial begin
    s = new();
    s.randomize();
    $display("%d",s.x);
  end
endmodule
2

x will be given a random value before the function gets called.

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