Function calls a function

SystemVerilog
,
1

Hi.
Suppose that I have two functions, which returns string.
Questa allows me to use the following syntax:
str = get_type_name().toupper();
According to LRM, I could not find if this is a legal or illegal syntax.
Other simulation tool does not allows this syntax, so I have to split the assignment into two assignments:
str = get_type_name();
str = str.toupper();

My question is: is the single-line assignment is legal according to LRM? Can you please referencs to the exact location in the LRM?

Thanks
Beeri

2

It’s not currently legal because the BNF does not support a function call as a legal part of a hierarchical selected name. See 404

Dave