In reply to chr_sue:
In reply to mseyunni:
There is not only ‘the answer’ because it depends on your environment and the rules and guidelines in your Company. And there are a lot of not answered questions.
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What is your C/C++ Code for?
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What is your current verification methodology?
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What is the size/complexity of your design?
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Do you have additional aspects to consider, like is your design algorithmic based?
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How many persons are involved in verification and design?
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etc.
What I recommend is also to use a UVM Framework Generator. Instead of the UVMF from Mentor I recommend the EasierUVM Framework Generator from Doulos. It is free-of-charge. Follow this link:
https://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm_generator/ -
We have C/C++ reference model to compare against the RTL
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UVM in general, but top level has a hybrid of C (and few other languages, scripts) and UVM.
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It is of size GPU
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Yes, the design is algorithmic in some parts.
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It is incremental design, we have about 2 designers and 2 verification engineers. I am trying to explore what would be the best possible method of verifying this complex design at top level. We have some unit level tb’s in UVM though.
Thanks,
Madhu