In reply to mseyunni:
There is not only ‘the answer’ because it depends on your environment and the rules and guidelines in your Company. And there are a lot of not answered questions.
- What is your C/C++ Code for?
- What is your current verification methodology?
- What is the size/complexity of your design?
- Do you have additional aspects to consider, like is your design algorithmic based?
- How many persons are involved in verification and design?
- etc.
What I recommend is also to use a UVM Framework Generator. Instead of the UVMF from Mentor I recommend the EasierUVM Framework Generator from Doulos. It is free-of-charge. Follow this link:
https://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm_generator/