Guys,
Trying to do something very simple. Obviously making a mistake. Newbie to SystemVerilog file I/O.
I have a binary data file called memFile.txt. It has only 1 line.
@0 11111111
I am trying to read this file using $fread (I know how to use $readmemb to do the same - but I want to use $fread).
Here’s my simple TB.
module fileIO;
int fd, status;
logic [15:0] mem [0:15];
logic [15:0] reg1;
initial begin
fd = $fopen ("memFile.txt", "rb");
//$readmemb ("memFile.txt", mem); //WORKS
//display ("mem[0] = %b",status,mem[0]);
status = $fread (reg1,fd); //DOES NOT WORK
$display ("status = %0d reg1 = %b",status,reg1);
$fclose(fd);
end
endmodule
Simulation Output:
status = 2 reg1 = 0100000000110000
Can’t figure out the simulation output.
Thanks for your help.