Frame Check Sequence or Parity Checker code in efficient way in SystemVerilog?

Hello Folks,

Can anyone comment on writing a short/effective way of coding the parity check or the frame check sequence that gets added along with any packet protocol for data integrity check ? Kindly share the same.

Thanks !

In reply to desperadorocks:

Can anyone comment on writing a short/effective way of coding the parity check or the frame check sequence that gets added along with any packet protocol for data integrity check ? Kindly share the same.

Parity check is defined in the requirements. Reduction XOR operator (e.g., ^data) or reduction XNOR operator (e.g., ~^data) can be used for parity of a data word.
For frame check sequence that gets added along with any packet protocol, it is typically a running sum (with overflow) of the data words in a packet, and that is checked against the sum that was provided in the packet. All of this should be specified in the requirements.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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