In reply to erictaur:
Does it really matter if sig** is toggling at the negedge as long as setup time is abided by? Besides, Formal verification does not handle setup and hold as this is done by a static timing analyzer tool. Thus, going back to the original question: Why the need for this assumption of the sig not toggling at the midway point?
Perhaps your intend if for the signal to be stable for 2 consecutive cycles, something like:
@(posedge clk) $changed(sig) |=> $stable(sig);
Ben