In reply to ben@SystemVerilog.us:
Hi Ben,
Thank you for responding!
Yes I did modify your snippet to be an assume property.
The signal in question, though being a primary input to the DUT, is actually flopped outside of the DUT – hence constraining that it should only be toggling / changing values at the posedge.
As far as I know, the DUT and the submodules within are operating on the posedge of the clock.
The behavior of the signal toggling at the negedge is most likely a result of the formal tool (VC-Formal to be exact)