In reply to erictaur:
I have a bit as a primary input to the DUT.
The only specification for this signal is that the value cannot change at the negative edge of the clock.
Sorry, you should have used the assume instead of the assert.
I still don’t understand why the signal toggles in mid-bit.
Do you have things toggling at both edges of the clock?
Why do you have this need to make this assumption?