Formal Verification SVA assume signal to NOT toggle at negedge

SystemVerilog
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4

In reply to ben@SystemVerilog.us:

In reply to ben@SystemVerilog.us:
I checked, Yes, multiclocking should be supported in general.
Ben

Hi Ben,

Thanks for your reply!

I have to add a -lca option to the elaborate command for this syntax to work but in the attached waveform, the signal is still toggling at the negative edge (as seen in marker intervals).

Link to screenshot