In reply to tri.nguyen1123:
If the assume is anywhere in the RTL model, even in individual checkers, it applies to all assertions.
Be careful here-- even if on states, outputs, etc, an assume’s requirements will be back-propagated to drivers.
Usually tools provide a way to create separate environments with different sets of assumptions if desired. Contact your vendor.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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