Formal arguments of a sequence/property in system verilog

I have a question on formal arguments passed to a sequence/property

  1. What are the formal argument types which can be passed to a sequence? In addition to data types, untyped, events and sequence are there any additional arguments possible?

  2. Just like passing parameters to modules or classes, can we pass parameters to the sequences which can be used for delays. This will help in making sequences more general.

  3. What are the formal arguments to the property? Can we pass another property as a formal argument to a property?

-sunil puranik

In reply to

1800’3027 page 1152 syntax answers your questions.
I prefer not to use arguments unless the sequences are reused, and I don’t see too much of that as they are generally specialized to address specific problems.
I also think that it is too complicated to pass a local variable from one sequence into another sequence instance; it’s hard to follow and I cannot guarantee that vendors actually implement all the features of SVA. KISS!
Delays and repeat numbers must be static and cannot depend on a variable.
My package addresses ways to use variables (see my signature for the link)
The answer to Q3 is Yes.

Ben Cohen
Link to the list of papers and books that I wrote, many are now donated.

or Cohen_Links_to_papers_books - Google Docs

Getting started with verification with SystemVerilog