Fork join_none disable block is not working

SystemVerilog
, ,
6

In reply to shamsheer:

What you see is a Simulator Issue probably

2 out of 3 Simulators give an Output ( which is I believe is correct ) ::

0 time C
2 time C
3 time D is 0

After the following changes ::


always @(*)
  begin
 
    if(i == 1)
    begin
        fork
          begin:A // Naming after begin instead of fork !!
        ...........

All 3 Simulators give Output ::

0 time C
2 time C
3 time D is 0