Fork-join inside always block

SystemVerilog
,
1

Hi,

I am executing the below code and the output is different than what I thought it would be.


  bit [15:0] a,b;
  bit clk;
  
  initial begin
    forever #5 clk = !clk;
  end

  always@(negedge clk) begin
    a= $urandom;
    b= $urandom;
  end

  always@(posedge clk) begin
    fork
      a = b;
      b = a;
    join
  end

What I thought would happen is , at every posedge of clk, both variables (‘a’,‘b’) will have same value and that value might be the value of ‘a’ (or) the value of ‘b’ (Because of race).

However, when I ran with different seeds and in every simulation, at posedge of clk, both variables (‘a’, ‘b’) are having value of ‘b’ .

The always block is acting as if fork-join is not present. Can anyone please explain why is this happening?

The code can be found at below EDA playground link:

Thanks in Advance,

2

In reply to dharani:

What you expected and what you are seeing are both valid outcomes. A race condition does not necessarily mean random behavior. It just means there is no guaranteed behavior.

Tools try to make sure results are repeatable to aid debug. In simulation, using a fork/join without any blocking statements is likely to be treated the same as begin/end.