Whenever rst1 is deasserted it should store register values.
if there is any change in register value in between this it should look for any change in register values and whenever there is change it should store updated value in array.
In between if reset get asserted array should hold stored values.i.e – value should not get updated to reset values.
Problem: In my simulation during first reset register value is changing in between 2 times. So, reg_instance. val_changed_e This should happen two times when register value is changing but its getting triggered only initially when the reset is deasseted.
All register threads are running in parallel but its missing 2nd register value change.
Could you please help why its happening even if all register threads are running in parallel?
reg regs[$]; // reg n field are all uvm ral model predefined classes
reg reg_instance;
field fields[$];
field fields_data[$];
field reg_fields[string][string];
task read_ register_fields();
forever begin
@(posedge rst1 iff rst1=== 1'b1) begin
foreach (reg_fields[register_name]) begin
fork
automatic string reg_name = register_name;
forever begin
@(reg_name. val_changed_e);predefined event
if (rst1=== 1'b1) begin
fork
foreach (reg_fields[reg_name][reg_field_wr]) begin
automatic string reg_field= reg_field_wr;
//reg_val = reg_instance.get();
reg_val = reg_fields[reg_name][reg_field].get();
store_reg_val[reg_field] = reg_val;
`pmc_info(("Register event happened:: reg_name:: %s, field_name:: %s , REG_VAL:: %x , STORE_VAL:::::%p\t", reg_name, reg_field, reg_val,store_reg_val));
end
join_none
end
end
join_none
end
end
end//forever
endtask:read_register_fields