Forever loop inside a fork-join_none

SystemVerilog
, ,
1

Hi,

I have a piece of code like the one below:


initial 
begin
if(testname !== "test_1")
begin : block1
$display("TRIAL1 at line = %0d instance = %m",`__LINE__);
fork 
	begin
		forever
			begin
				@(posedge flag2);					
				$assertkill(0, top_tb.tb_file1.sb_if.ap_1);
				`uvm_info("",$sformatf("TRIAL1 Entered at line = %0d Testcase name = %s at time = %t instance = %m",`__LINE__,testname,$realtime),UVM_LOW)
		
					                
			end
	end
	begin
		if(stop)
			begin				
				$display("TRIAL1 block1 disabled at time = %t",$realtime);
	        	        disable block1;
			end
	end

join_none
end : block1


if(testname !== "test_1")
begin : block2
$display("TRIAL2 at line = %0d instance = %m",`__LINE__);
fork
	begin
		forever
			begin
		
				@(negedge flag2);
				$asserton(0,top_tb.tb_file1.sb_if.ap_1);	
				`uvm_info("",$sformatf("TRIAL2 Entered at line = %0d Testcase name = %s at time = %t instance = %m",`__LINE__,testname,$realtime),UVM_LOW)
				
					
			end
	end
        begin
		if(stop)
			begin
				$display("TRIAL2 block2 disabled at time = %t",$realtime);
				disable block2;
			end

	end  

join_none
end : block2
end

Question: I’m seeing that TRIAL1 and TRIAL2 statements are getting printed. For the simulation that i’m running any one of the two @(posedge flag2) or @(negedge flag2) would definitely get executed. With this i should be able to see the uvm_info print statement on my log. But i'm not seeing the print statement at all from the uvm_info. I’m also not seeing this print statement : $display(“TRIAL2 block2 disabled at time = %t”,$realtime); and $display(“TRIAL2 block2 disabled at time = %t”,$realtime);.

I’m just not understanding why the `uvm_info statements are not getting printed.

I appreciate any insights you can provide.

Regards,
Ritvik

2

In reply to Ritvik Kumar:

You have not shown enough information about how flag2 and stop get stimulated to reproduce your issue. I presume you want wait(stop) instead of if(stop).