Foreach within class

SystemVerilog
, ,
1 
class packet;
  bit [7:0] a;
  rand bit [7:0] b;
  bit [7:0] c;
  bit [7:0]j;
foreach(b[i])
c[i] == 2**i;

endclass
 
module inline_constr;
  initial begin
    packet pkt;
    int i;
    pkt = new();
    //pkt.b = 8'b10010000;
    //pkt.j=8'h00;
    //pkt.add();
    //repeat(10) begin

    //pkt.randomize();

    foreach(pkt.c[i]) 
      $display("Value of b = %0d",pkt.c);
    //end
  end
endmodule

Its throws following error
SystemVerilog keyword ‘foreach’ is not expected to be used in this context.

In class, is it not possible to use foreach and i see error while assigning variables with class on = sign.
Could you comment on this.

2

In reply to Sreega Curie:

The foreach construct can only be used as a statement inside a procedural block of code or as a random constraint. Your second foreach is correctly inside a procedural initial block.

If you meant it as a constraint, see section 18.5.8.1 foreach iterative constraints in the IEEE 1800-2017 SystemVerilog LRM
Constraints are made of boolean expressions, not assignments.