Foreach Loop

SystemVerilog
1 
 foreach(payload[i]) begin
    bytes[i + 22] = payload[i];
    $display("bytes[22 + %d]=%d and payload=%d",i,bytes[22 + i],payload[i]);
  end
$display("::::::::::::::::::::::::");

In this given code I want to assign payload to my method bytes but it shows value 0 only after executing as I am writing pack method and I want to do this.

2

In reply to Hardik Trivedi:
please show the declarations of all variables involved.

3

In reply to dave_59:

In reply to Hardik Trivedi:
please show the declarations of all variables involved.

class ethernet_packet;

rand bit [55:0] preamble;
rand bit [7:0] sfd;
rand bit [47:0] d_addr;
rand bit [47:0] s_addr;
rand bit [15:0] d_length;
rand logic unsigned payload;
rand bit [31:0] crc;

constraint pre_c {preamble==56’hAAAAAAAAAAAAAA;}
constraint sfd_c {sfd==8’b10101011;}
constraint len_c {d_length>=46;d_length<=1500;}
constraint pay_c {payload.size()==d_length;}
// constraint order_c {solve d_length before payload;}

function disp();
$display($time," preamble =\t%b", preamble);
$display($time," sfd =\t%b", sfd);
$display($time," d_addr =\t%h", d_addr);
$display($time," s_addr =\t%h", s_addr);
$display($time," d_length =\t%d", d_length);
$display($time," payload_size =\t%d", $size(payload));
$display($time," payload =\t", payload);
$display($time," crc =\t%h", crc);
endfunction

virtual function int unsigned byte_pack(ref logic [7:0] bytes);
//int i=0;
bytes = new[payload.size + 24];
{>>{bytes}} = {preamble,sfd,d_addr,s_addr,d_length};

foreach(payload[i]) begin
bytes[i + 22] = payload[i];
$display(“bytes[22 + %d]=%d and payload=%d”,i,bytes[22 + i],payload[i]);
end
$display(“::::::::::::::::::::::::”);
// {>>{bytes[22 + payload.size()]}};

byte_pack = bytes.size;

endfunction : byte_pack

endclass

module top;
ethernet_packet pkt=new;
logic [7:0] bytes;
int load;
initial begin
pkt.randomize();
pkt.disp();
pkt.byte_pack(bytes);
$display(“\n Packed DATA :”,bytes);
$display(“\n packet.size :”,bytes.size);
end
endmodule

4

In reply to Hardik Trivedi:
Did you meant to declare payload as

 rand logic [7:0] payload[];

Then you could have just defined byte_pack as

virtual function int unsigned byte_pack(ref logic [7:0] bytes[]);
  {>>{bytes}} = {preamble,sfd,d_addr,s_addr,d_length, payload};
  return bytes.size;
endfunction : byte_pack