Foreach in constraints

SystemVerilog
,
1

constraint range {foreach (a[i]) (i<31) → a[i+1]=~a[i];}

while using the abve statement , it throws the following error
near “=”: syntax error, unexpected ‘=’, expecting ++ or –

please tell the reason

2

Syntax is wrong . Syntax should look like this
for constraint assignment it should be used == instead of =
You should use the

constraint range {foreach (a[i]) (i<31) -> (a[i+1]==a[i]);}
3

In reply to kddholak:

thank u so much