Forcing random value into signals

SystemVerilog
, ,
1

Hi, I am trying force the signals to random value which will change at each loop. I read somewhere that class data cannot be passed into force/assign the signals. So, I tried to create static signal to passed the random value into it. However, the static forced_value do not take random_value. How can I force my signals to get the random value? I have check that random_value actually get randomized.

Here is my code.

class connectivity extend test;
     rand bit[2399:0] random_value;
     constraint c {random_value<2;}
     static bit[2399:0] forced_value;
     ...

     task run_phase(uvm_phase phase);
          phase.raise_objection(this);
          super.run_phase(phase);

          force top.reset = 0;
          #50ns;
          force top.reset = 1;
          #50ns;
          for (int i = 0; i < 100; i++) begin
              forced_value = this.randomize(random_value);
              force top.a0.r_a1_0.signal_0 = forced_value[0];
              force top.a0.r_a1_0.signal_1 = forced_value[1];
              force top.a0.r_a1_0.signal_2 = forced_value[2];
              force top.a0.r_a1_0.signal_3 = forced_value[3];
              force top.a0.r_a1_0.signal_4 = forced_value[4];
              ...
              ...
              ...
              i = i + 1;
              #50ns;
          end
     endtask: run_phase
endclass: connectivity
2

In reply to ashlanK:

Hi,

this.randomize() returns a status value, not the randomized value about whether the randomize function was successful or not.

Change your code to be like this:
this.randomize(random_value);
forced_value = random_value;
…

Brian