Forcing hierarchical nodes through tasks

SystemVerilog
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4

In reply to sohil08:

Are you using this task in any class?


task check(ref logic a,b,c);
static s_a, s_b,s_c;
s_a = a ;
s_b = b ;
s_c = c ;
force a = s_a;
force b = s_b;
force c = s_c;
endtask