Forcing hierarchical nodes through tasks

SystemVerilog
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2

In reply to sohil08:

Did you tried using ref as input argument of task.

task check(ref logic a,b,c);
force a = 0;
force b = 1;
force c = 0;
endtask

// calling task
for (i=0;i<=n;i++)
begin check(RTL_HIER.a[i],RTL_HIER.b[i],RTL_HIER.c[i]);
end