Force is not working for fault injection in verilog

SystemVerilog
, , , ,
1

I wanted to do functional fault testing on a small circuit, like this:

    module logic2(
	input wire a,
	input wire b,
	input wire c,
	input wire e,
	output wire y,
	output wire z
	);

wire d, f, g, h, j, k, w, x, p, q;
assign f = d;

or gate1(d, a, b);
and gate2(p, d, e);
not gate3(g, p);
or gate4(j, g, h);
nand gate5(w, b, j);
and gate6(x, j ,g);
not gate7(q, f);
nor gate8(k, q, c);

// final outputs
and gate9(z, w, x);
or gate10(y, k, a);




endmodule

I was using force-release on the wires for the submodule in the top module, but it just gives the correct output and doesn’t force the wires. I tried not passing sel to top, and just assigning it values inside the top module itself, but it still doesn’t seem to work.

I have been looking through the forums a lot and haven’t been able to find the problem. I am using iverilog for this. Here is the top module and testbench if that helps:

module top(
	input wire [4:0] sel,
	input wire control,
	input wire a,
	input wire b,
	input wire c,
	input wire e,
	output wire y,
	output wire z
	);

logic2 circ(a, b, c, e, y, z);

initial begin

	if(sel==5'b00000) begin
		// do not force
	end
		
	if(sel==5'b00001) begin
		force circ.a = control;
	end
	
	if(sel==5'b00010) begin
		force circ.b = control;
	end
    
    if(sel==5'b01010) begin
		force circ.k = control;
	end


end

endmodule

module testbench;

reg in1, in2, in3, in4;
wire o1, o2;
wire v1, v2;
reg [3:0] testval;
reg [4:0] sel;
reg control;

integer i, stuck, node;
integer scan1;
integer tb_file1;

top circ_fault(sel, 1'b0, in1, in2, in3, in4, o1, o2);
logic2 circ_verify( in1, in2, in3, in4, v1, v2);

initial begin

$dumpfile("logic2_tb.vcd");
$dumpvars;
	

tb_file1=$fopen("testcases_exhaustive.txt", "r");
	

for(i=0; i<16; i=i+1) begin
	scan1 = $fscanf(tb_file1, "%b\n", testval);
	$display("\nTestcase: %d %b", i+1, testval);

	in1 = testval[3];
	in2 = testval[2];
	in3 = testval[1];
	in4 = testval[0];

	$display("Expected: %d%d", v1, v2);		

	for(node=1; node<=16; node=node+1) begin
		sel = node;
		for(stuck=0; stuck<=1; stuck=stuck+1) begin
			if(stuck==0) begin
				control = 1'b0;
			end
			if(stuck==1) begin
				control = 1'b1;
			end
			
			#20
			if( (o1!=v1)||(o2!=v2) ) begin
				$display("node:%d, sa%d ", node, stuck);
			end
			//$display("o1o2 %d%d v1v2 %d%d", o1, o2, v1, v2);


		end
	end
end 

$finish;

end
endmodule