Dear Forum,
Please help to resolve one issue related to forcing signals of top instance, using bind command.
So I need to connect the testbench to one of instances in my top RTL. And I am using bind for it.
Everything will go well if there is no one but …
My top module drives the same signals that the TB tries to drive them. As a result I am getting X-s on that signals.
To resolve this I can use force and force the instance inputs to my interface signals, however not sure that this is the best option.
Could you please provide some suggestions?
Here is example code for your reference:
module fifo(input in_dut, output out_dut);
endmodule
module dut_top(
input FPGA_CLK100M_P,
input FPGA_CLK100M_N,
input LOGIC_RESETn, // Active LOW !!!
input CLOCK_PRESENT
);
wire fifo_in, fifo_out;
fifo u_TIFIFO (
.in_dut(fifo_in),
.out_dut(fifo_out)
);
// Here top module drives the u_TIFIFO instance pins, which I need to be controlled by TB
initial
begin
fifo_in = 1'b1;
#5 fifo_in = 1'b0;
#5 fifo_in = 1'b1;
end
assign fifo_out = 1'bz;
endmodule
interface itf (
output reg fifo_in,
input fifo_out
);
endinterface
module tb(itf itf_inst);
initial // drives the fifo instance pins
begin
itfInst.in_dut = 1'b0;
#5 itfInst.in_dut = ~itfInst.in_dut;
#5 itfInst.in_dut = ~itfInst.in_dut;
end
endmodule
module top();
wire in,out;
dut_top dutInst ();
itf itfInstncTI (in, out);
bind fifo itf itf_inst(.fifo_in(in_dut),.fifo_out(out_dut));
tb tbInst (dutInst.u_TIFIFO.itf_inst);
endmodule