Force a DUT signal from a systemverilog class

In reply to chr_sue:

If you need to do a ‘force’ statement, then what I would do is this:
a) create a 2-bit GPIO agent/driver at top-level testbench that you from your UVM test environment. One bit selects between ‘drive’ and ‘release’, the other is the value to be driven.
b) the GPIO output will trigger a bit of code that will do the ‘drive’ and ‘release’.
c) that bit of code will do a cross-module reference and drive your internal signal.

I’ve not tried doing ‘forces’ from within ‘bind’ statements - not saying they won’t work, but I’ve found that the tool vendors don’t rigorously test things that nobody uses. So I try to stick to the usual methods. And you’ll have to do the same GPIO and bit of force/release logic.