Force a DUT signal from a systemverilog class

UVM
13

In reply to chr_sue:

Hi,

  1. UVMF is not a tool feature; it’s a library of source-code classes. So it will run in Cadence, Synopsys, etc.
  2. My proposal doesn’t rely on UVMF anyways - I just happened to mention it, in case that helped clarify things. I’m sorry to have brought it up - please ignore it.
  3. Do you agree that drivers are implemented with a class-instance in an environment, and a module/interface instance in a testbench?