Force a DUT signal from a systemverilog class

In reply to erik.k.jessen@raytheon.com:

You mewan with UVMF the Mentor UVM Framework generator. Right?
But moving from 1 company to another on makes the problem when you are relying on tool features. If the new company has a different simulator you are runninmg into serious problems. And you will n ot do this using language features.