For loop running infinitely

SystemVerilog
,
1

I ran the below code and it keeps on running. can anyone explain this? why does it keep on running?


module top; 
  initial begin 
    for(bit [1:0]i=0;i<4;i++)
    begin 
      $display("Loop is executed"); 
    end  
  end  
endmodule
2

In reply to Arvind Tiwari:

You are using the two-bit variable ā€˜iā€™ as the loop variable. A two-bit variable can have the values 0,1,2 and 3, and will loop from 3 to 0 when incremented. The maximum value of 3 is less than 4, so the loop termination condition is never met, so the loop is infinite.

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