For loop in system verilog

When a signal array gets blasted into individual signal bits, like \primary_sig[0], \primary_sig[1], \primary_sig[3], etc, you cannot use a variable to index into that signal because it is no longer an array. Because of the , all the characters that follow become part of the signal name and the [0] at the end of the name has lost its meaning and is just part of the identifier name.

You will have to manually access each bit, or use a script to generate the code

primary_sig[0] = test_bench.dut.u_top.u_chip_core_top.u_security_control_wrapper.u_security_control.\primary_sig[0] ;
primary_sig[1] = test_bench.dut.u_top.u_chip_core_top.u_security_control_wrapper.u_security_control.\primary_sig[1] ;